PicLA: a very low cost Logic Analyzer

New: Version 2.0 (sep 2009)

Overview

This page describes a very low cost logic analyser using an 18F2525 PIC microprocessor and a PC. The PIC is used as a hardware capture device which monitors the datalines and records all changes. The buffering, triggering, interpretation and display is handled by a PC program running under Windows. The hardware cost will vary between €15 (RS232 version) and € 30 (USB version). The analyser can operate in a "Fast Sampling" mode, in which the data is sampled into an internal 1K buffer on the PIC and in "Normal Sampling" or "Continious Sampling " mode in which all data changes are offloaded to the PC in real time and arbritary sampling buffer size is available.
A short specification

• User selectable sampling of 2, 4 or 8 channels.
• "Fast Sampling" at 5 MHz / 2 MHz / 1 MHz / 500 kHz, 200 kHz and 100 kHz giving resolutions of 200nSec to 10 uSec.
• "Normal Sampling" at 500 kHz, 200 kHz, 100 kHz and 50 kHz giving resolutions of 2 uSec to 20 uSec.
• 3840, 7680 or 15360 samples can be stored in "Fast sampling" mode (depends on 8, 4 or 2 bit mode)
  Also in the 500 kHz and slower rates the memory can be compressed, increasing the maximum capture time dramatically.
  
• In "Normal Sampling" there is no limit to the duration of the trace, the current version supports up to 50 seconds.
• A 256-Event burst buffer is used if the data lines change faster than the data can be transmitted to the PC
• PC Link limits the "average" speed of the logic analyser (The nr. of transitions that can be recorded per second) in normal mode
• Average limit for 8bit "Normal sampling": 3840 events/sec (115kBit) or 15000 events/sec (500kBit).
• Average limit for 4bit "Normal sampling": 5760 events/sec (115kBit) or 25000 events/sec (500kBit).
• Average limit for 2bit "Normal sampling": 11520 events/sec (115kBit) or 50000 events/sec (500kBit).

History

More and more chips I used in one experiments required the usage of chips which were controller using some kind of serial protocol. This varied from the AD9832 Digitital Synthesiser, reading RFID tags, the HTRC1000 HiTag read chiper chip, various digital thermometers and the whole range of I2C chips.
Although an oscilloscope was sometimes helpful the tedious job of writing small test program's to write to the chip in repeated loops to get an stable picture of what was going on a logic analyser would be far better.

Although a logic analyser is a nice instruments, for hobby purposes they are in my opinion way to expensive. Prices are starting with a few thousand Euros.
Cheaper options are the "PC-based" logic analysers which are normally connected to the USB, serial or parallel port of a PC. The PC takes care of displaying the the data and the actual sampling is done by dedicated hardware which is controlled by a microcontroller. These devices can capture data in the MegaHertz range and have a memory capacity ranging from a few K samples up to 256K samples. Some examples of these logic analysers are:

• The Bitscope project which will also give you a Digital Storage Scope.
• The RockyLogic 8bit Logic Analyser.

These devices will cost you a few hunderd Euros and are a good alternative.

A fews years ago I purchased a "software logic analyser", SoftLA from bgmicro. This used the PC's printer port as inputs and ran under DOS. The timing was however not very accurate and due to the various flavours of the parallel port (Standard, EPP, ECP) you could run into problems on some systems (like my laptop)

Because of earlier projects with various PIC microcontroller from MicroChip I wondered how fast I could sample the I/O lines and make my own "very low cost" logic analyser". It was easy to sample the I/O lines at a rate of 1 MHz but the memory capacity of these devices is rather limited, from a few hundred bytes up to a few kilobytes.

The next step was to use the the PIC (an 16F628) as the "sample" engine which sampled the I/O lines and send the events (change on one of the input lines) which occurred to a PC over a serial interface. Al the processing (triggering / display / protocol analysis) would be offloaded to the PC. So apart from advanced trigger options this also implies that a very large number of samples can be taken: moderm PC offer megabytes of available RAM. Some fiddling with a 20 MHz 16F628 microcontroller showed that I could sample data at 10 microsecond intervals (100 kHz sample rate) and had time left to offload the data to the PC using the serial interface. The hardware requirements are a PIC16F628 and Maxim 232 level convertor plus the additional capacitors and crystal. Less than € 10 in hardware costs.

One big problem is that it is not possible to send the events at the sample rate to the PC: the maximum rate of the serial devices is normally limited to 115kBaud which limits the number of events the serial interface can handle to about 5700 / seconds. The "average" pulse width should therefore be larger than 200 microseconds. Before the data is send to the PC it is kept in a ringbuffer on the microcontroller, so it is possible to buffer small bursts. The size of the buffer depends on the type of microcontroller used. So the resolution / sampling rate of the logic analyser is a lot better than the sustained rate of events it can handle.

Although a 10 microsecond sample interval is workable in a lot of situations it would be nice to support faster sampling rates as well. I2C has e.g. a datarate of 100kHz or 400kHz. The next version used one of the new 18F chips (the 18F252). This processor runs twice as fast, has a smarter instruction set and more memory onboard. This allowed me to increase the fastest sampling time to 2 microseconds and add an additional 4 data lines so an 8 channel logic analyser was a possible. The increased memory size was helpfull in enlarging the "Burst buffer" from 64 to 256 events. To improve the "sustained" data rate the RS-232 interface was replaced with an FDTI FT232BM chip and the transfer speed was changed to 500 kilobit/second. Although 1 Mbit is possible this caused a problem with the VCP driver on the PC side, it could not keep up with the data. The current version can handle up to 25.000 events/sec, giving an average pulse with of 40 uSec.

Finally a "FAST Sampling" mode was added. Although the available RAM on the microprocessor limits the trace duration the sampling rate can now be increased to 5 MHz (200 nanosecond sampling interval). Although triggering options are limited in this mode, it can be useful when e.g. checking an interface to an HD44780 LCD display where you want to monitor signals with sub-microsecond resolution. (Which was the reason for this addition to the logic analyser). In the slower rates only changes on the datalines are saved, enlarging the maximum capture time up to 256 fold.

• A 18F252/2525 based capture device LOGAN18
• The PC software to use the capture device: PicLA

September 2009 update

• Updated website with new schematic/sources/executables
• Removed refererences to the 12 MHz version (1Mbit serial link)
  

June 2009 update (PicLA Version 2.00, LOGAN18 version 6)

• Memory compression added in 2, 5 and 10 microsecond FAST mode
  In FAST mode you can now select to compress the memory by storing only line-changes. This allows recording of up to 3840 events in this mode. The compression varies with the depth of the data, in 8bit mode a 256X compression can be reached, in 4bit mode a 16X compression and in 2bit mode a 64X compression. Compression should always be used if the sample clock is 2X higher than the maximum data rate of the expected signals.
• You can now specify a delay (from 0 to 65535 microsignals) between the start trigger and the start of the sampling.
  

March 2009 update (PicLA Version 1.20, LOGAN18 version 5)

In the new version the following changes were made:

• New 2 bit sampling mode for monitoring SPI/I2C/CANbus.
• New sampling rates in "fast" mode: 5 and 10 microsecond.
• The application has a slighty larger trace window (but still not resizable).
• Bug fix: 4bit sampling at 20usec mode did not work.
  
• Bug fix: timing was 10% of in 4bit 2usec fast sampling.
  
• Larger sample buffer: In 8 bit mode an additional 256 samples can be taken, in 4bit mode 512 additional samples, in 2bit mode 1024.
• In "Fast" Sampling a new triggering mechanism is added: a START trigger. One time events could be missed due to the method which was used for trigger detection: Sample/Search/Sample/Search. If the trigger occured during the search phase it was missed. With the new trigger type the system waits for the trigger before the sampling starts.
• "External Trigger Input" in FAST. A separate "Trigger input" (PORTC bit 3) can also be used to start the sampling.
• The capture device has additional commands to allow monitoring of up to 8 serial lines and up to 19200 Baud.
  To use this option you will need the "Serial Spy" program on the PC.

Still to do

The logic analyser is evolving over time as most of the functionality is implemented in software on a PC. A new feature gets added when I need it for some project.
Some planned and partially implemented features are:

• Finishing the 2 bit mode for NORMAL sampling
• Cleanup the windows program, some functions which are not active are currently not disabled
• Improve the "Abort" mechanism in FAST mode, you now have to wait until the unit times out (which can be up to 5 seconds)
  
• Implement support for the analog channels and add a low-frequency digital storage scope (up to a 100kHz) or voltage recorder.
• Update the schematics for External trigger and Serial line Monitoring

Limits of the current version

PE1GRL